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is64lp12832 is64lp12836 issi ? integrated silicon solution, inc. ? 1-800-379-4774 1 rev. 00c 07/12/04 copyright ? 2004 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control interleaved or linear burst sequence control using mode input three chip enables for simple depth expansion and address pipelining common data inputs and data outputs jedec 100-pin tqfp and 119-pin pbga package power-down snooze mode power supply + 3.3v v dd + 3.3v or 2.5v v ddq (i/o) temperature offerings option a2: -40 0 c to +105 0 c option a3: -40 0 c to +125 0 c description the issi is64lp12832 and is64lp12836 are high-speed synchronous static rams designed to provide high-perfor- mance memory with burst for high-speed networking and communication applications. is64 lp12832 is organized as 131,072 words by 32 bits. is64lp12836 is organized as 131,072 words by 36 bits. the is64lp12832 and is64lp12836 are fabricated with issi 's advanced cmos technology. these devices integrate a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. bw1 controls dqa, bw2 controls dqb, bw3 controls dqc, bw4 controls dqd, conditioned by bwe being low. a low on gw input would cause all bytes to be written. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. preliminary information july 2004 fast access time symbol parameter -150 units t kq clock access time 4.3 ns t kc cycle time 6.7 ns frequency 150 mhz 128k x 32, 128k x 36 synchronous pipelined static ram
is64lp12832 is64lp12836 issi ? 2 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 block diagram 17 binary counter bw1 gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 15 17 address register ce d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bw4 ce ce2 ce2 bw2 bw3 128k x 32/128k x 36 memory array 32 or 36 input registers clk output registers clk 32 or 36 oe 4 oe dq a-d (x32/ x36) (x32/ x36) (x32/ x36) (x32/ x36) 32 or 36 a
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. 00c 07/12/04 is64lp12832 is64lp12836 issi ? pin configuration pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address ad- vance bw1 - bw4 individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequ ence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable nc dqb dqb vddq gnd dqb dqb dqb dqb gnd vddq dqb dqb gnd nc vdd zz dqa dqa vddq gnd dqa dqa dqa dqa gnd vddq dqa dqa nc a a ce ce2 bw4 bw3 bw2 bw1 ce2 vdd gnd clk gw bwe oe ads c adsp adv a a nc dqc dqc vddq gnd dqc dqc dqc dqc gnd vddq dqc dqc nc vdd nc gnd dqd dqd vddq gnd dqd dqd dqd dqd gnd vddq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd vdd nc nc a a a a a a a 46 47 48 49 50 128k x 32 100-pin tqfp
is64lp12832 is64lp12836 issi ? 4 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 pin configuration pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bw1 - bw4 individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o a b c d e f g h j k l m n p r t u vddq nc nc dqc1 1 dqc2 2 vddq dqc5 5 dqc7 7 vddq dqd1 1 dqd4 4 vddq dqd6 6 dqd8 8 nc nc vddq a6 6 ce2 a7 7 dqpc dqc3 3 dqc4 4 dqc6 6 dqc8 8 vdd dqd2 2 dqd3 3 dqd5 5 dqd7 7 dqpd a5 5 nc nc a4 4 a3 3 a2 2 gnd gnd gnd bw3 gnd nc gnd bw4 gnd gnd gnd mode a10 1 0 nc adsp adsc vdd nc ce oe adv gw vdd clk nc bwe a1 a0 vdd a11 1 1 nc a8 8 a9 9 a12 1 2 gnd gnd gnd bw2 gnd nc gnd bw1 gnd gnd gnd nc a14 1 4 nc a16 1 6 ce2 a15 1 5 dqpb dqb6 6 dqb5 5 dqb4 4 dqb2 2 vdd dqa7 7 dqa5 5 dqa4 4 dqa3 3 dqpa a13 1 3 nc nc vddq nc nc dqb8 8 dqb7 7 vddq dqb3 3 dqb1 1 vddq dqa8 8 dqa6 6 vddq dqa2 2 dqa1 1 nc zz vddq 1 2 3 4 5 6 7 dqpb dqb dqb vddq gnd dqb dqb dqb dqb gnd vddq dqb dqb gnd nc vdd zz dqa dqa vddq gnd dqa dqa dqa dqa gnd vddq dqa dqa dqpa a a ce ce2 bw4 bw3 bw2 bw1 ce2 vdd gnd clk gw bwe oe ads c adsp adv a a dqpc dqc dqc vddq gnd dqc dqc dqc dqc gnd vddq dqc dqc nc vdd nc gnd dqd dqd vddq gnd dqd dqd dqd dqd gnd vddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd vdd nc nc a a a a a a a 46 47 48 49 50 128k x 36 119-pin pbga (top view) 100-pin tqfp
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. 00c 07/12/04 is64lp12832 is64lp12836 issi ? truth table address operation used ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l xxxx high-z deselected, power-down none l l x l xxxx high-z deselected, power-down none x x h h l x x x high-z deselected, power-down none x l x h l x x x high-z read cycle, begin burst external l h l l xxxxq read cycle, begin burst external l h l h l x read x q write cycle, begin burst external l h l h l x write x d read cycle, continue burst next x x x h h l read l q read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h xxxhlreadlq read cycle, continue burst next h xxxhlreadh high-z write cycle, continue burst next x x x h h l w rite x d write cycle, continue burst next h xxxhlw rite x d read cycle, suspend burst current x x x h h h read l q read cycle, suspend burst current x x x h h h read h high-z read cycle, suspend burst current h xxxhhreadlq read cycle, suspend burst current h xxxhhreadh high-z write cycle, suspend burst current x x x h h h w rite x d write cycle, suspend burst current h xxxhhw rite x d partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bw1 bw1 bw1 bw1 bw1 bw2 bw2 bw2 bw2 bw2 bw3 bw3 bw3 bw3 bw3 bw4 bw4 bw4 bw4 bw4 read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes h lllll write all bytes l xxxxx
is64lp12832 is64lp12836 issi ? 6 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 interleaved burst address table (mode = v dd or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ddq + 0.3 v v in voltage relative to gnd for ?0.5 to v dd + 0.5 v for address and control inputs v dd voltage on v dd supply relative to gnd ?0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. 00c 07/12/04 is64lp12832 is64lp12836 issi ? operating range 3.3v (i/o) 2.5v (i/o) range ambient temperature v dd v ddq v ddq a2 ?40c to +105c 3.3v, +10%, ?5% 3.3v, +10%, ?5% 2.5v + 5% a3 ?40c to +125c 3.3v, +10%, ?5% 3.3v, +10%, ?5% 2.5v + 5% dc electrical characteristics (1) (over operating range) 2.5v (i/o) 3.3v (i/o) symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = ?4.0 ma (3.3v) 2.0 ? 2.4 ? v i oh = 1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) ? 0.4 ? 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 1.7 v dd + 0.3 2.0 v dd + 0.3 v v il input low voltage ?0.3 0.7 ?0.3 0.8 v i li input leakage current gnd v in v dd ?5 5 ?5 5 a i lo output leakage current gnd v out v ddq ,?5 5 ?5 5 a oe = v i power supply characteristics (over operating range) -150 symbol parameter test c onditions max. unit i cc ac operating device selected, a2 280 ma supply current all inputs = v il or v ih a3 290 ma oe = v ih , v dd = max. cycle time t kc min. i sb standby current device deselected, a2 80 ma v dd = max., a3 90 ma all inputs = v ih or v il clk cycle time t kc min. i zz power-down mode zz = v dd a2 20 ma current clock running a3 25 ma all inputs gnd + 0.2v or v dd ? 0.2v notes: 1. the mode pin has an internal pullup. this pin may be a no connect, tied to gnd, or tied to v dd . 2. the mode pin should be tied to v dd or gnd. it exhibits 10 a maximum leakage current when tied to gnd + 0.2v or v dd ? 0.2v.
is64lp12832 is64lp12836 issi ? 8 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 3.3v i/o output load equivalent output z o = 50 ? 1.5v 50 ? 317 ? 5 pf including jig and scope 351 ? output +3.3v figure 1 figure 2
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. 00c 07/12/04 is64lp12832 is64lp12836 issi ? 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1ns input and output timing 1.25v and reference level output load see figures 3 and 4 2.5v i/o output load equivalent output z o = 50 ? 1.25v 50 ? 1,667 ? 5 pf including jig and scope 1538 ? output +2.5v figure 3 figure 4
is64lp12832 is64lp12836 issi ? 10 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 read/write cycle switching characteristics (over operating range) -150 symbol parameter mi n. max. unit f max (3) clock frequency ? 150 mhz t kc (3) cycle time 6.7 ? ns t kh clock high time 2.6 ? ns t kl (3) clock low time 2.6 ? ns t kq (3) clock access time ? 4.3 ns t kqx (1) clock high to output invalid 3.0 ? ns t kqlz (1,2) clock high to output low-z 0 ? ns t kqhz (1,2) clock high to output high-z 1.5 3.5 ns t oeq (3) output enable to output valid ? 4.2 ns t oeqx (1) output disable to output invalid 0 ? ns t oelz (1,2) output enable to output low-z 0 ? ns t oehz (1,2) output disable to output high-z 2.0 3.5 ns t as (3) address setup time 2.0 ? ns t ss (3) address status setup time 1.5 ? ns t ws (3) write setup time 1.5 ? ns t ces (3) chip enable setup time 2.0 ? ns t avs (3) address advance setup time 1.5 ? ns t ah (3) address hold time 1.0 ? ns t sh (3) address status hold time 1.0 ? ns t wh (3) write hold time 1.0 ? ns t ceh (3) chip enable hold time 1.0 ? ns t avh (3) address advance hold time 1.0 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2. 3. tested with load in figure 1.
integrated silicon solution, inc. ? 1-800-379-4774 11 rev. 00c 07/12/04 is64lp12832 is64lp12836 issi ? read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bw4-bw1 bwe gw a adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b
is64lp12832 is64lp12836 issi ? 12 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 write cycle switching characteristics (over operating range) -150 symbol parameter mi n. max. unit t kc (1) cycle time 6.7 ? ns t kh (1) clock high time 2.6 ? ns t kl (1) clock low time 2.6 ? ns t as (1) address setup time 2.0 ? ns t ss (1) address status setup time 1.5 ? ns t ws (1) write setup time 1.5 ? ns t ds (1) data in setup time 1.5 ? ns t ces (1) chip enable setup time 2.0 ? ns t avs (1) address advance setup time 1.5 ? ns t ah (1) address hold time 1.0 ? ns t sh (1) address status hold time 1.0 ? ns t dh (1) data in hold time 1.0 ? ns t wh (1) write hold time 1.0 ? ns t ceh (1) chip enable hold time 1.0 ? ns t avh (1) address advance hold time 1.0 ? ns note: 1. tested with load in figure 1.
integrated silicon solution, inc. ? 1-800-379-4774 13 rev. 00c 07/12/04 is64lp12832 is64lp12836 issi ? write cycle timing single write data out data in oe ce2 ce2 ce bw4-bw1 bwe gw a adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
is64lp12832 is64lp12836 issi ? 14 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 snooze and recovery cycle switching characteristics (over operating range) -150 symbol parameter mi n. max. unit t kc (3) cycle time 6.7 ? ns t kh (3) clock high time 2.6 ? ns t kl (3) clock low time 2.6 ? ns t kq (3) clock access time ? 4.3 ns t kqx (1) clock high to output invalid 3.0 ? ns t kqlz (1,2) clock high to output low-z 0 ? ns t kqhz (1,2) clock high to output high-z 1.5 3.5 ns t oeq (3) output enable to output valid ? 4.2 ns t oeqx (1) output disable to output invalid 0 ? ns t oelz (1,2) output enable to output low-z 0 ? ns t oehz (1,2) output disable to output high-z 2 3.5 ns t as (3) address setup time 2.0 ? ns t ss (3) address status setup time 1.5 ? ns t ces (3) chip enable setup time 2.0 ? ns t ah (3) address hold time 1.0 ? ns t sh (3) address status hold time 1.0 ? ns t ceh (3) chip enable hold time 1.0 ? ns t zzs zz standby 2 ? cyc t zzrec zz recovery 2 ? cyc notes: 1. guaranteed but not 100% tested. this parameter is periodically sampled.
integrated silicon solution, inc. ? 1-800-379-4774 15 rev. 00c 07/12/04 is64lp12832 is64lp12836 issi ? snooze and recovery cycle timing single read high-z high-z data out data in zz oe ce2 ce2 ce bw4-bw1 bwe gw a adv adsc adsp clk rd1 1a read snooze with data retention t kc t kl t kh t ss t sh t as t ah rd2 t ces t ceh t ces t ceh t ces t ceh t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz t zzs t zzrec
is64lp12832 is64lp12836 issi ? 16 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00c 07/12/04 ordering information temperature range (a2): ?40c to +105c speed order p art no. organi zation package 150 mhz is64lp12832-150tqa2 128kx32 tqfp IS64LP12836-150TQA2 128kx36 tqfp temperature range (a3): ?40c to +125c speed order p art no. organi zation package 150 mhz is64lp12832-150tqa3 128kx32 tqfp is64lp12836-150tqa3 128kx36 tqfp is64lp12836-150ba3 128kx36 pbga
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/12/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic ball grid array package code: b (119-pin) notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e do not include mold flash protrusion and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches sym. min. max. min. max. n0. leads 119 a ? 2.41 ? 0.095 a1 0.50 0.70 0.020 0.028 a2 0.80 1.00 0.032 0.039 a3 1.30 1.70 0.051 0.067 a4 0.56 bsc 0.022 bsc b 0.60 0.90 0.024 0.035 d 21.80 22.20 0.858 0.874 d1 20.32 bsc 0.800 bsc d2 19.40 19.60 0.764 0.772 e 13.80 14.20 0.543 0.559 e1 7.62 bsc 0.300 bsc e2 11.90 12.10 0.469 0.476 e 1.27 bsc 0.050 bsc e1 a1 d1 7654321 a b c d e f g h j k l m n p r t u e2 e a2 seating plane e d2 d a 30 ? a3 a4 b (119x)
integrated silicon solution, inc. ? 1-800-379-4774 packaging information issi ? pk13197lq rev. d 05/08/03 tqfp (thin quad flat pack package) package code: tq thin quad flat pack (tq) millimeters inches millimeters inches symbol min max min max min max min max ref. std. no. leads (n) 100 128 a ? 1.60 ? 0.063 ? 1.60 ? 0.063 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011 d 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874 d1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791 e 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638 e1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555 e 0.65 bsc 0.026 bsc 0.50 bsc 0.020 bsc l 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030 l1 1.00 ref. 0.039 ref. 1.00 ref. 0.039 ref. c0 o 7 o 0 o 7 o 0 o 7 o 0 o 7 o notes: 1. all dimensioning and tolerancing conforms to ansi y14.5m-1982. 2. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 do include mold mismatch and are determined at datum plane -h-. 3. controlling dimension: millimeters. d d1 e e1 1 n a2 a a1 e b seating plane c l1 l

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